1. Field of the Invention
The present invention relates to a method for producing a semiconductor device and a semiconductor device.
2. Description of the Related Art
Semiconductor integrated circuits, in particular, integrated circuits that use MOS transistors, are continuing to achieve ever higher integration density. Due to increasing integration density, MOS transistors used therein have been miniaturized to a nanometer scale. Increasing miniaturization of MOS transistors renders it difficult to suppress leak current and a problem has arisen in which the area occupied by the circuit cannot be decreased due to the need to obtain a required amount of current. In order to address this issue, a surrounding gate transistor (hereinafter referred to as an SGT) has been proposed, in which a source, a gate, and a drain are arranged in a direction perpendicular to the substrate and a gate electrode surrounds a pillar-shaped semiconductor layer (for example, refer to Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
According to a typical method for producing an SGT, a silicon pillar having a pillar-shaped nitride film hard mask is formed by using a mask for forming a silicon pillar, a planar silicon layer is formed at a bottom of the silicon pillar by using a mask for forming the planar silicon layer, and a gate line is formed by using a mask for forming the gate line (for example, refer to 2009-182317). In other words, three masks are used to form a silicon pillar, a planar silicon layer, and a gate line.
A metal-gate-last process in which a metal gate is formed after a high-temperature process has been employed in actual production of typical MOS transistors in order to integrate a metal gate process and a high-temperature process (refer to IEDM 2007, K. Mistry et. al, pp 247-250). A gate is formed by using polysilicon, an interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing and etched, and then a metal is deposited. Thus, a metal-gate-last process in which a metal gate is formed after a high-temperature process must be employed in making SGTs in order to integrate a metal gate process and a high-temperature process.
In a metal-gate-last process, a diffusion layer is formed by ion implantation after formation of a polysilicon gate. Special consideration is necessary for SGTs since the upper portion of the pillar-shaped silicon layer is covered with a polysilicon gate.
As silicon pillars become thinner, it becomes increasingly difficult to allow an impurity to exist in the silicon pillars since the density of silicon is 5×1022 atoms/cm3.
According to a proposal (for example, refer to Japanese Unexamined Patent Application Publication No. 2004-356314) related to typical SGTs, the threshold voltage is determined by changing the work function of the gate material while decreasing the impurity concentration in the channel to 1017 cm−3 or less.
It has been shown that the impedance of an LDD region of a planar MOS transistor can be decreased compared to oxide film side wall LDD-type MOS transistors if the side wall of the LDD region is formed by using a polycrystalline silicon having the same conductivity type as the low-concentration layer. This is because the surface carriers of the LDD region are induced by the difference in work function (for example, refer to Japanese Unexamined Patent Application Publication No. 11-297984). This patent document shows that the polycrystalline silicon side wall is electrically insulated from the gate electrode and that an interlayer insulating film insulates the polycrystalline silicon side wall from the source and drain as illustrated in the drawings.
In a typical MOS transistor, a first insulating film is used to decrease parasitic capacitance between the gate line and the substrate. For example, in a FINFET (refer to IEDM 2010 CC. Wu, et. al, 27.1.1-27.1.4), a first insulating film is formed around one fin-shaped semiconductor layer and etched back to expose the fin-shaped semiconductor layer in order to decrease parasitic capacitance between the gate line and the substrate. Accordingly, the first insulating film is desirably used in forming an SGT in order to decrease parasitic capacitance between the gate line and the substrate. Since an SGT includes a pillar-shaped semiconductor layer in addition to a fin-shaped semiconductor layer, consideration is needed in forming the pillar-shaped semiconductor layer.